| Manufacturer | WIZNET |
| IC | Ethernet controller |
| Mounting | SMD |
| Operating temperature | -40...85°C |
| Communictions protocol | ARP, IGMP, IPv4, PPPoE, TCP, UDP |
| Symbol | Communictions protocol | Features | Interface | Supply voltage | Case | TX/RX buffer size | Channels | Max. frequency | Memory | Number of inputs/outputs | Kind of architecture | 32bit timers | Memory | Kind of core |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| [V DC] | [MHz] | [kB] | [kB] | |||||||||||
| W55RP20 | ICMP | DMA; PHY; TCP/IP | - | 1.8...3.3 | - | - | - | - | - | - | - | - | - | |
| W55RP20-S2E | ICMP | DMA; PHY; TCP/IP | - | 1.8...3.3 | - | - | - | - | - | - | - | - | - | - |
| W5300 | ICMP | DMA; MAC; PHY; TCP/IP | 8/16bit BUS | 3.3 | LQFP100 | 128 kB | 8 | - | - | - | - | - | - | - |
| W5100 | ICMP | MAC; PHY; TCP/IP | 8bit BUS; SPI | 3.3 | LQFP80 | 16 kB | 4 | - | - | - | - | - | - | - |
| W5100S-L | ICMP | MAC; PHY; TCP/IP | 8bit BUS; SPI | 3.3 | LQFP48 | 16 kB | 4 | 70 | - | - | - | - | - | - |
| W5100S-Q | ICMP | MAC; PHY; TCP/IP | 8bit BUS; SPI | 3.3 | QFN48 | 16 kB | 4 | 70 | - | - | - | - | - | - |
| W6100-L | ICMPv4, ICMPv6, IPv6, MLDv1 | MAC; PHY | 8bit BUS; SPI | 3.3 | LQFP48 | 16 kB | 8 | 25 | - | - | - | - | - | - |
| W6100-Q | ICMPv4, ICMPv6, IPv6, MLDv1 | MAC; PHY | 8bit BUS; SPI | 3.3 | QFN48 | 16 kB | 8 | 25 | - | - | - | - | - | - |
| W7500P-S2E | ICMP | MAC / PHY; TCP/IP | ADC; I2C x2; MII; RS232C; RS422 / RS485; SPI x2; SWD; TTL; UART x3 | 2.7...5.5 | TQFP64 | 32 kB | 8 | 48 | 128 | 53 | Cortex M0 | 4 | 48 SRAM | 32-bit |
| W7500-S2E | ICMP | MAC; TCP/IP | ADC; I2C x2; MII; RS232C; RS422 / RS485; SPI x2; SWD; TTL; UART x3 | 2.7...5.5 | TQFP64 | - | 8 | 48 | 128 | 53 | Cortex M0 | 4 | 48 SRAM | 32-bit |
| W7500 | ICMP | MAC; TCP/IP | ADC; I2C x2; MII; SPI x2; SWD; UART x3 | 2.7...5.5 | TQFP64 | - | 8 | 48 | 128 | 53 | Cortex M0 | 4 | 48 SRAM | 32-bit |
| W7500P | ICMP | MAC / PHY; TCP/IP | ADC; I2C x2; MII; SPI x2; SWD; UART x3 | 2.7...5.5 | TQFP64 | 32 kB | 8 | 48 | 128 | 53 | Cortex M0 | 4 | 48 SRAM | 32-bit |
| W5200 | ICMP | MAC; PHY; TCP/IP | SPI | 3.3 | QFN48 | 32 kB | 8 | - | - | - | - | - | - | - |
| W5500 | ICMP | MAC; PHY; TCP/IP | SPI | 3.3 | LQFP48 | 32 kB | 8 | - | - | - | - | - | - | - |